Hi,
I am experiencing some problem in using TSR to implement a lock.
I have written a test case where I access TSR for "core 0" (from core 0). At beginning I set TSR to “1” so that next read-access will read "1" and lock is granted. Then I write “0” to release it (as done in RCCE). But the problem is I can acquire a lock but then program stops there unless I write a value to TSR using “flit widget” (using sccGui).
Another question, from RCCE_admin.c
Semantics of test&set register: a read returns zero if another core has previously read it and no reset has occurred since then. Otherwise, the read returns one.
Does reset means that the core that previously read it writes to TSR?
Am I missing something here?
I have attached my code as well.
Thank you